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Extra resources for Economic strategy for developing nuclear breeder reactors
30]): in ADCs the redundancy is used to alleviate the effect of comparator mismatch, whereas in DACs, the redundancy is used to alleviate the effect of current source mismatch. Also note that, independently from this work, prior art on sub-binary radix DACs exists , but that work does not mathematically optimize the redundancy, uses a fixed instead of a variable radix, and requires a more complex measurement method. In the following sections, the design of the DAC core with redundancy, the self-measurement structure and the digital pre-correction algorithm will be explained.
The main components (serial-in/parallel-out register, switch driver, switches and CSA) will be discussed next. 4 V only. The selection of the low supply has two reasons: first, it will prove that the DAC design allows low-voltage operation while maintaining sufficient linearity, which is a necessity for future low-voltage technologies. Secondly, the DAC will be used as an on-chip test-signal generator for the T&H (see Chapter 7). 15 V, which is suitable for the T&H. 1 Serial-in parallel-out register Because of pin limitations, the 16-bit data-input is provided through a serial interface: 16 clock pulses on the Serial clock input are required to load a 16-bit P.
This algorithm is performed iteratively for the sources 1 up to k − 1. At the end of the measurement loop, all weights are scaled to normalize the range to the full-scale range of the N -bit input-code. 6. Algorithm, finding a combination of sources approximating source j. Analog measurement circuit The analog part of the measurement setup has to provide the digital algorithm with the sign information of Δj . In , a two-step approach is used. First the value of Ij is recorded on a variable current source (implemented as a subbinary DAC).